Low Power Computing Paradigms Based on Emerging Non-Volatile Nanodevices

G.-F.Wang,W.Kang,Y.-Q.Cheng,J.Nan,J.-O.Klein,Y.-G.Zhang,and W.-S.Zhao

1.Introduction

Power consumption has become a major issue as the integrated circuits(IC)coming into the deep submicron(<90 nm) nowadays.According to International Technology Roadmap for Semiconductors(ITRS),the static power will occupy a high percentage of the cost in the future[1].The traditional digital processing approaches are based on the complementary metal oxide semiconductor(CMOS)technology,which suffers from both high static and dynamic power consumption at the deep submicron[2].The von Neumann architecture consumes much power on memory access and reading/writing the data compared with that on logic operations(e.g.～1 pJ and ～1 fJ,respectively at 22 nm node)as shown in Fig.1[3],[4].In that case,we focus on the improvement of memories,which is the main power consumer.Because of using the intrinsically volatile silicon memories,data in the “idle” state should be always kept under an uninterrupted power supply,which leads to high static power.As the feature size scales down,the power consumption will grow dramatically and dominate the whole consumption of digital IC.Efforts on overcoming the power dissipation and building up the next generation IC have been started in early 2000s[5].Among them,emerging nanodevices have promising prospects to become the workhorse of the next generation low power electronics.Researches on these fields are promoted by some significant technological advances of nanodevices[6]-[10].In this paper,we present the state-of-the-art on emerging nanodevices and discuss their potentials on building novel computing systems.In addition,we also review the neuromorphic circuit system design by using nanodevices.

This paper first introduces several kinds of emerging nanodevices currently under considerable investigation,such as the memristor,spintronics,multiferroic devices,and tunnel-field effect transistor(tunnel-FET)from the power saving and data retention perspectives.In the following section,we give a compact introduction of the novel computing paradigms.The normally-off circuit,logic in memory architecture,reconfigurable computing logic circuit,and non-volatile nanodevice based neuromorphic circuit are presented in order.These paradigms can be very different from the traditional computing structures on power consumption and data processing which are influenced by the emerging nanodevices.The next part concludes these paradigms and discusses the prospect of nanodevices research and development.We give the conclusions of this paper at last.

Fig.1.Volatile cache memories used for data access acceleration leads to high static power.Data access between CPU core and main memory consumes much higher than that of MOSFET transistor switching.

2.Emerging Nanodevices for Computing Systems

Surpassing the silicon-based devices,many nanodevices,such as nanowires,quantum dots,memristors,spintronics,and grapheme,have their own advantages[6]-[14].In order to reduce the power consumption,the non-volatility and the ultra-low leakage current are mainly considered as the most two outstanding factors.In addition,higher electron mobility,as an important characteristic,means a faster transformation among different states,which could enhance the device operating speed.Thus,nanodevices can be classified into the following three categories accordingly.

The so called “dark silicon”[15]is expected to be provided in the next generation IC by using the non-volatile and memristive nanodevices for the data storage.The static power can be considerably reduced,because the part of chip in the “idle” state can be powered off completely[16].The non-volatility and tunable resistance of the nanodevices have been proposed thanks to the new technology,such as memristors,spintronics,and multiferroic devices.

2.1 Memristors

The memristor was originally proposed in 1971 as a missing non-linear passive two-terminal electrical component relating electric charge and magnetic flux linkage.Four fundamental two-terminal circuit elements:resistor(R),capacitor(C),inductor(L),and memristor(M)are shown in Fig.2[17].Note that R,C,L,and M can be functions of the independent variable in their defining equations,yielding nonlinear elements.Different from a linear resistor,M has a dynamic relationship between the current and voltage including a memory of past voltages or currents.According to the governing mathematical relations,the electrical resistance of a memristor is not constant but depends on the history of current flowing through it,i.e.its current resistance depends on how much and in which direction the electric charges has flowed through in the past.Thus,when the electric power turns off,the memristors hold its most recent resistance until the power turn on again.The principle of a memristor device is shown in Fig.3[10].The width of doped part can be changed by the current.Different widths of doped area are corresponding to the different resistance.There are two extreme states:ROFFand RON,where ROFFstate means the lowest dopant concentration and highest resistance while RONstate has the highest concentration of dopants and lowest resistance.

2.2 Spintronics

The spin of the electron is an angular momentum intrinsic to the electron that is separated from the angular momentum due to its orbital motion.It is well known that the electron possesses both the charge and spin properties.In classical electronics,electric fields move the charges to transmit information.However,in magnetic recording,we utilize the magnetic fields to read or write the information stored on the magnetization,which measures the local orientation of spins in ferro-magnets[7].The local orientation of spins has two states known as up and down,providing two binary states to the conventional low and high logic values.Spintronics technology has been applied in many storage components such as magnetic random access memory(MRAM)and hard disks due to its higher data transfer speed,greater processing power,increased memory density,and increased storage capacity.

The magnetic tunnel junction(MTJ)is the most important device of spin-based integrated circuits.An MTJ is mainly consists of three layers:two ferromagnetic(FM)layers(e.g.,CoFeB)and one insulating barrier(e.g.,MgO)(see Fig.4).The electrons travel from one FM layer to the other due to the tunneling effect.It can present two resistance values(RPor RAP)depending on the relative magnetization orientations of the two ferromagnetic layers.The two states:parallel(P)and anti-parallel(AP)correspond to the two resistances,respectively.The different resistances are characterized by the tunnel magneto-resistance(TMR)ratio shown as

Generally,one of the FM layers is pinned while the other is free.We use an external magnetic field or a spin polarized current to switch the orientation of spins in the free layer.Fig.5 shows a direct current(DC)simulation of MTJ under a 28 nm node.We use a voltage to change the state and the resistance can be controlled as RPor RAP.

Fig.2.Four fundamental two-terminal circuit elements:resistor,capacitor,inductor,and memristor.

Fig.3.Principle of memristor device.

Fig.4.Non-volatile and memristive nanodevices:magnetic tunnel junction composed of ferromagnetic and oxide thin films.

Fig.5.DC simulation of the PMA MTJ/CMOS hybrid circuit to validate the correctness of the spice model,under 28 nm node.

In order to get a better thermal stability,future work will focus on the perpendicular magnetic anisotropy MTJ(PMA MTJ)which means the orientation of the spins in the FM layer is perpendicular to the barrier layer.The behavior of PMA-MTJ switching is mainly determined by the threshold or critical current IC0which is shown as

where E is the barrier energy that separates the two magnetization directions depending on the saturation magnetic field Msand the shape anisotropy field HK,V is the volume of free layer of MTJ nanopillar,α is the magnetic damping constant,γ is the gyromagnetic ratio,e is the electron charge,Bμ is the Bohr magnetron,and g is the spin polarization efficiency factor.The switching duration of PMA-MTJ is dependent with the switching current Iwritevalue,as shown in(3):

where τ is the switching duration,C is Euler’s constant,andis the activation energy in the unit of kBT(kBis the Boltzmann constant and T is the temperature).Prefand Pfreeare the tunneling spin polarizations of the reference and free layers,M is the magnetic moment of the free layer.

Fig.6.Simulation of PMA-MTJ.Iwriteis the current pass through the MTJ.V is the voltage of MTJ.When state=1.0 the MTJ switches to the RPstate; and when state=0 the MTJ switches to the RAPstate.

Fig.7.Write current as a function of cell width for STT-MRAM.

According to these equations,we can calculate the switching energy of a specific PMA-MTJ such as CoFeB/MgO/CoFeB MTJ,as shown in Fig.6.The mean switching energy can be ～0.95 pJ under the 45 nm node.Equation(2)gives the relationship between the threshold current IC0and the volume of free layer.As the technology node shrinks to the 22 nm node today,the volume reduces which causes reduction of the switching threshold current.In that case,IC0will reduce and the duration decrease at the same time.In the spin-based integrated circuits(e.g.,STT-MRAM),the switching energy is mainly decided by MTJs.In another word,the power consumption of these circuits will decrease with the technology node scaling down as plotted in Fig.7.

2.3 Multiferroics

Multiferroics implies the materials that exhibiting more than one ferroic characteristic simultaneously such as coexistence of ferromagnetism,ferroelectricity,and ferro-elasticity.The multiferroic coupling allows the switch of ferroelectric states,so it is considered to hold great potential for many applications[18].Particularly,in multiferroic thin films,the coupled magnetic and ferroelectric order parameters can be applied for developing magnetoelectronic devices including novel spintronics devices,such as tunnel magnetoresistance sensors and spin valves.For the tunnel magnetoresistance devices,they consist of two layers of ferromagnetic materials separated by a thin tunnel barrier made of multiferroic thin film[19].The multiferroic effect in such a device separates the spin electron in each ferromagnetic layer so that the spin transport across the barrier can be electrically tuned.Moreover,the multiferroic layer can also be used as the exchange bias pinning layer.If the antiferromagnetic spin orientations in the multiferroic pinning layer can be tuned electrically,the magnetoresistance of the device can be controlled by an external electric field[20].Except for building tunnel magnetoresistance devices,multiferroic can also be used for multiple level cell(MLC)memories,where data are stored both in the electric and the magnetic polarizations.

2.4 Other Low Leakage Devices

As mentioned above,the leakage currents that leak through silicon transistors make a main contribution to the static power consumption.For the past few years,many researchers spend large efforts to reduce the leakage currents,such as using the strained silicon,high-κ dielectrics,stronger doping levels,and new device structures[2].Among them,the tunnel field-effect transistor(TFET)is a new type of metal-oxide-semiconductor field-effect transistor(MOSFET),shown in Fig.8(a),using the high-κ material instead of the silicon dioxide gate.It is a P-I-N(p-type,intrinsic,n-type)diode where the intrinsic region is controlled by the gate.The barrier width for carriers tunneling from the source to the channel and traveling to the drain can be modulated by the gate voltage.When the barrier width becomes less than 10 nm,electrons can tunnel from the source valance band into the channel conduction band,and then the tunneling current flows.During this process,Ioffis composed of the P-I-N diode reverse bias current and leakage current[21].It has a large gate capacitance and ultra-low leakage.The benefits of the TFET are particularly linked to its roughly flat sub-threshold curve when Vddscaling down.However,TFET also have some disadvantages like the low Ionand immature fabrication process.

Fig.8.Low leakage current and high electron mobility transistors:(a)ultra low Ioffnanodevices:Si-channel based tunnel FET(TFET)and(b)nanodevice with high mobility channel:Graphene FET(GFET)transistor.

As the operating frequency of computing systems increases up to several GHz,it faces a limitation even though the feature size scaling can continue,i.e.,the chip power budget.One of the solutions is to increase the electron mobility and then reduce the operating duration.The high mobility devices including graphene-based FET(GFET)become the preferred new devices due to its excellent mobility which could be larger than that of silicon by one order of magnitude(Fig.8(b))[8].

These nanodevices can not only be compatible with traditional CMOS processes but also help relaxing the power wall for future deep submicron ICs.In that case,they become the most attractive devices to the semiconductor industries[22],[23].Furthermore,as the novel devices promise high maturity and low power cost because of their compatibility and non-volatility,investigators demonstrate that they have many significant advantages to become the most potential devices to dominate the next generation IC compared with the post-silicon nano-electronics.However,the relative lower speed and larger die area compared with silicon memories are two limited factors.For instance,MTJ,widely used in STT-MRAM,is one of the most fast non-volatile and memristive devices.However,the switching time is limited to some nanosecond in the state-of-the-art research[7].That means it is necessary to propose some novel computing paradigms different from the conventional ones,which can integrate the new devices.Meanwhile,it is also important to make a good tradeoff between low power and high performance at the system level[24].

3.Novel Computing Paradigms Based on Non-Volatile Nanodevices

Emerging devices are so different from the traditional CMOS technology so that novel computing paradigms must be proposed to exploit their potentials.At the same time,power reduction,area efficiency,and speed enhancement are the requirements to the next generation very large scale integrated circuites(VLSI).As the novel computing paradigms can integrate non-volatile memristive nanodevices to save power and reduce the die area,some architectures presented in the past are now revisited[25]-[27].Furthermore,proper system design has to adapt to the unique properties of the emerging devices so that the power consumption can be reduced as much as possible.

3.1 Normally-Off Computing Technology

Normally-off computing is a novel concept which is proposed for being dramatically different from the conventional “normally-on” system.The conceptual method of the new computing system is very simple:the control system can partially activate the logic blocks according to the workload and manage the power dissipation as shown in Fig.9[28].When the central processing unit(CPU)is in the standby state,the information is stored in the non-volatile memories built by emerging nanodevices.When the system is reset,the data stored in non-volatile memories can be automatically recalled in the registers or flip-flops in a very short time.

For example,Qualcomm proposed the full integration of STT-MRAM to build up an ultra-low power computing system shown in Fig.10[29].Full integration is a kind of solution to take full advantage of non-volatile nanodevices.However,as the access speed and write power of STT-MRAM are worse than those of the static random access memory(SRAM)or flip-flops in the processor core,the full integration may degrade the clock frequency and increase dynamic power.Toshiba proposed a partial integrate system structure(see Fig.10),in which only the level 2 and level 3 cache memory and main memory are replaced by perpendicular magnetic anisotropy spintransfer-torque MRAM(PMA STT-MRAM)[30].The authors claimed that the power consumption would be reduced over 80% without any performance degradation for real applications running on mobile CPUs.

3.2 Logic in Memory

Integration of emerging non-volatile memories with CMOS to build up logic circuits has been intensely investigated in the last years and a number of successful prototypes based on the logic in memory architecture have been demonstrated[31],[32].As shown in Fig.11,it is generally composed of four parts:a sense amplifier(S.A)to evaluate the logic result,a non-volatile memory block(e.g.,MRAM and memristor),a write circuit to program the non-volatile memory,and a volatile MOS logic block.This type of logic circuits is the most popular one currently and draws considerable attention due to its good compatibility with conventional computing architectures and easy integration with the existing MOS technology process.Thanks to the vertical structure of the non-volatile storage devices(e.g.,MTJ and memristor),they can be fabricated above the CMOS circuits at the back-end process.This 3D integration structure shortens greatly the data traffic distance between the memory and logic chips,thus accelerating greatly the logic computing speed and saving significantly the dynamic power.To realize the logic in memory,many hybrid logic building blocks have been proposed in the past few years,such as the non-volatile flip-flop(NVFF)[33],[34],full adder(FA)[31],and look-up table(LUT)[16].Other advantages of logic in memory circuits are their instant on/off capability,nearly zero standby power,and hardness to power failure.However,they also suffer from some challenges which need to be addressed.For example,the switching latencies(several nanoseconds)of the non-volatile memories are much larger than those of the conventional MOS logic circuits,which limit the computing frequency to the GHz range.Another severe issue is the poor sense reliability caused mainly by the device mismatch of the S.A[35].Different from the memory circuits where complex error correction circuits(ECCs)[36]can be employed,it is difficult to embed them in the logic circuits while keeping the fast speed,small area,good reliability,and high power efficiency.

Fig.9.Concepts of partially activating the logic blocks:(a)all logic blocks are busy(red),(b)all most half of them are in standby state(gray),and(c)all the logic blocks are in standby state,in which power consumption is zero[28].

Fig.10.Novel system structures:(a)full integration of STT-MRAM for ultra low computing system proposed by Qualcomm[29] and(b)partial integration to replace L2 or L3 cache memory and main memory proposed by Toshiba[30].

Fig.11.Logic in memory structure with two inputs A and B.This structure include the sense amplifier,CMOS logic,non-volatile memory,and write circuit.

3.3 Reconfigurable Computing Logic Circuits

The field programmable gate arrays(FPGA)is known as the reconfigurable computing logic circuits which advances rapidly in last twenty years due to its remarkable advantages in research and development(R&D)costs[37].However,the traditional reconfigurable computing logic is still not satisfied with the growing market of application specific logic circuits(ASIC)because of the low power efficiency and logic density.All the functions have to be pre-programmed and stored into SRAM before the FPGA power-up every time,while when a power failure occurs all the data will be lost.External non-volatile memories are integrated into the chip either in the same package or at the printed circuit board(PCB)level,which are used to store the functions.When the FPGA power turns on,the functions stored in the memories can be used to program.To keep the configuration data,the static power becomes high due to the rapidly increasing leakage currents as mentioned in previous sections.It is difficult for the conventional logic blocks to become dynamically reconfigurable when it uses the volatile shift register or SRAM to store the configuration.Moreover,getting the configuration data from the non-volatile memory out of the chip takes too much time(e.g.～1 ms).Facing so many disadvantages,traditional reconfigurable computing circuits require a new way to deal with the static functions and intermediate data storage.The non-volatile technology should be applied to reduce the standby power and it can supply the fast data access(e.g.<1 ns)to ensure the fast reconfiguration and computing speed.For these reasons,various non-volatile RAMs are invented,such as STT-MRAM,thermally assisted switching based MRAM(TAS-MRAM)and Fe-RAM which are under intense investigation to be integrated in reconfigurable logic systems[38]-[40].

The runtime reconfiguration(RTR)logic block allows to reduce the number of logic computing blocks,thereby relaxing the power and area constraints of the FPGA.Fig.12 is a MRAM-based non-volatile FPGA which can perform RTR reconfiguration with nearly zero standby power and “instant-on” start-up.

Fig.13 gives an example of a racetrack memorybased[41]reconfigurable logic circuit under the 28 nm CMOS design kit,where W is the distance between constrictions and M is the diameter of MTJ nano pillar.MTJ 1-8 are the read heads associated to the magnetic nanowire.The logic circuit with three inputs is firstly programmed to “AND” logic and then reconfigured dynamically to “XOR” logic.Instead of taking milliseconds in the conventional reconfigurable logic circuits,this process of reconfiguration can be very fast,a few hundred nanoseconds is enough.The computing speed is ～500 ps if the output is not protected for a high-speed propose,which means the computing frequency of this LUT can reach to GHz.Benefited from the non-volatile storage device,the power is relatively low:the energy for “AND” logic configuration is ～1.37 pJ(including the domain wall propagation and nucleation dissipation)and the energy for“XOR” logic reconfiguration is ～1.95 pJ.The energy for computing is as low as ～28.6 fJ per operation[42].

3.4 Non-Volatile Nanodevices Based Neuromorphic Circuit

For several years,researchers have been designing“neuromorphic” circuits that work analogously to the brain[43],[44].Such circuits could allow a form of intelligent and ultra-low power computing(the brain can solve problems inaccessible for supercomputers within only 20 W).However,fabricating neuromorphic systems with pure CMOS has severe limitations,since they require massive and ideally non-volatile memories for their neurons and“synapses”.Nanoscale memristive devices,such as the memristor[10],ferroelectric memristor[45],and spintronic memristor[46],are the most promising candidates as the synapse in neuromorphic systems.Nanoscale memristive devices adjust their resistance depending on which voltage is applied to them,so they are indeed reminiscent,which is similar to synapses[47](the connections between neurons in the brain).It suggests they could be used as synapses.Additionally,the possibility to integrate them as crossbars offers promises of extremely high integration,and thus massive connectivity.

Fig.12.Mask of MRAM-based FPGA logic circuit prototype[38].

Fig.13.Example of a racetrack memory-based reconfigurable logic circuit:(a)hybrid racetrack memory and CMOS circuit to build a non-volatile LUT for reconfigurable computing and(b)symbol of this RM-LUT[42].

Envision the nanoscale memristive devices based circuits as a reconfigurable unit cell that will not be programmed but trained,named supervised neuromorphic networks,following ideas coming from the neural network field[48].Logical functions can then be trained to the circuit,in the same way an artificial network is trained with a dataset[49].With such an approach,high robustness to variability and defects can be achieved with small overhead.The basic algorithm behind this approach had been experimentally demonstrated on the small scale with the carbon nanotube based devices(the neural network learning rule was demonstrated)[50].More work is needed to build real systems.An even more radical approach is to develop models of calculation that do not rely on traditional logic,named unsupervised neuromorphic networks,escaping usual paradigms[50].Such networks are not programmed as usual systems,but are instead able to infer regularities in data presented to them,and can perform cognitive-type functions.A vision to achieve that is the imitation of actual biological synapses.It has been suggested and shown experimentally that nanoscale memristive devices could reproduce spike timing dependent plasticity(STDP),a behavior of synapses of the brain[51].

Neuromorphic circuits with nanoscale memristive devices can be implemented with asynchronous CMOS technology and has very promising prospects.We hope that by extending it to more devices and more complicated architectures,extremely complex tasks could be accomplished with a limited energy budget.We believe that this approach is especially suitable to categorize natural data,and could in particular provide smart low power sensors for embedded systems.In the long term,such an approach opens the door of cognitive computing and computers with real intelligence which is a goal now pursued by several visionary projects.

4.Discussion and Perspective

Besides the aforementioned nanodevices,many other novel technologies are proposed for different computing paradigms such as spin-FET.They have already been applied on some computing systems or logic circuits,as shown in Table 1.

Table 1:Applications of several novel devices[52]

The non-volatile nanodevices are widely used in the emerging computing circuits which may dominate the future computer system.The normally-off computing system which was proposed by Toshiba could reduce over 80% power consumption compared with the traditional CMOS system in the same performance.Apart from the zero standby power,the normally-off computing structure can also make a great progress in its size by using the high density non-volatile memories like MRAM.Due to the good compatibility with conventional CMOS circuit architectures,non-volatile nanodevices are easily to be integrated in the existing logic circuits.Therefore,the logic in memory structure has been one of the most popular design methodologies.The instantly on/off capability which also means hardness to power failure,nearly zero standby power,and many other advantages make them possible to be applied in some new architectures which are radically different from the standard von-Neumann architecture.The non-volatile nanodevices can offer ultra-low standby power,high density,and the non-volatility which are all needed to construct a reconfigurable logic(e.g.MRAM- based FPGA).These features of the nanodevices enable that they are suitable for being integrated in reconfigurable logic computing to ensure a fast reconfiguration and overcoming the data missing when the power cuts off.For the emerging computing paradigms such as neuromphics,the nonvolatile nanodevices can also find its favorable position for the use of their advantages.

However,these novel computing paradigms are not mature yet.For instance,the switching latency of the MTJ circuits is much larger than those of conventional CMOS logic circuits,which may limit the computing frequency.The poor sensing reliability causes more read failure than the CMOS based logic circuits,thus the reliability of these computing structures become a main problem.Although,much work focuses on these hurdles,more suitable solutions are still needed to overcome these shortage before practical applications.More and more novel nanodevices and emerging computing paradigms will come into view in the near future.

5.Conclusions

In this paper,we firstly give an overview of emerging non-volatile nanodevices and the novel computing paradigms based on them.The novel computing paradigms are under intense investigations since they have many advantages over traditional CMOS circuits.The mentioned emerging non-volatile nanodevices are classified in terms of working principles and fabricating materials.The potential applications of these devices in novel computing systems and the resulting circuit design paradigm shift are also discussed with illustrative examples.Finally,we give a discussion on the prospects of the novel nanodevices and the emerging computing paradigms.

[1](July 2012).Int.Technology Roadmap for Semiconductors.[Online].Available:http://www.itrs.net.

[2]N.S.Kim,T.Austin,D.Baauw,T.Mudge,K.Flautner,J.-S.Hu,M.J.Irwin,M.Kardemir,and V.Narayanan,“Leakage current:Moore’s law meets static power,” Computer,vol.36,no.12,pp.68-75,2003.

[3]J.Backus,“Can programming be liberated from the von Neumann style?:A functional style and its algebra of programs,” Communications of the ACM,vol.21,no.8,pp.613-641,1978.

[4]K.Ramaiya,V.Shrinivasan,and S.Bhargava,“Architecture,design and development of a green ICT system,” in Green Technologies:Concepts,Methodologies,Tools and Applications,New York:IGI Global,2010,pp.268.

[5]D.B.Strukov and K.K.Likharev,“CMOL FPGA:a reconfigurable architecture for hybrid digital circuits with two-terminal nanodevices,” Nanotechnology,vol.16,no.6,pp.888-900,2005.

[6]A.DeHon,“Array-based architecture for FET-based,nanoscale electronics,” IEEE Trans.on Nanotechnology,vol.2,no.1,pp.23-32,2003.

[7]C.Chappert,A.Fert,and F.N.Van Dau,“The emergence of spin electronics in data storage,” Nature Materials,vol.6,no.11,pp.813-823,2007.

[8]F.Schwierz,“Graphene transistors,” Nature Nanotechnology,vol.5,no.7,pp.487-496,2010.

[9]G.Agnus,W.-S.Zhao,V.Derycke,A.Filoramo,S.Lenfant,D.Vuillaume,et al.,“Carbon nanotube programmable devices for adaptive architectures,” in Proc.of the 10th Trends in Nanotechnology Int.Conf.,Barcelona,2009,pp.1667-1670.

[10]D.B.Strukov,G.S.Snider,D.R.Stewart,and R.S.Williams,“The missing memristor found,” Nature,vol.453,no.7191,pp.80-83,2008.

[11]J.B.N.J.Wang,J.B.Neaton,H.Zheng,V.Nagarajan,S.B.Ogale,B.Liu,and R.Ramesh,“Epitaxial BiFeO3 multiferroic thin film heterostructures,” Science,vol.299,no.5613,pp.1719-1722,2003.

[12]W.-S.Zhao,G.Agnus,V.Derycke,A.Filoramo,J.P.Bourgoin,and C.Gamrat,“Nanotube devices based crossbar architecture: toward neuromorphic computing,”Nanotechnology,doi:10.1088/0957-4484/21/17/175202.

[13]M.Kabir,M.R.Stan,S.A.Wolf,R.B.Comes,and J.Lu,“RAMA:a self-assembled multiferroic magnetic QCA for low power systems,” in Proc.of the 21st ACM Great Lakes Symposium on VLSI,Lausanne,pp.25-30,2011.

[14]J.Borghetti,G.S.Snider,P.J.Kuekes,J.J.Yang,D.R.Stewart,and R.S.Williams,“ ‘Memristive’ switches enable‘stateful’ logic operations via material implication,” Nature,vol.464,no.7290,pp.873-876,2010.

[15]N.Goulding-Hotta,J.Sampson,G.Venkatesh,S.Garcia,J.Auricchio,P.-C.Huang,et al.,“The GreenDroid mobile application processor:An architecture for silicon’s dark future,” IEEE Micro,vol.31,no.2,pp.86-95,2011.

[16]W.-S.Zhao,E.Belhaire,C.Chappert,and P.Mazoyer,“Spin transfer torque(STT)-MRAM--based runtime reconfiguration FPGA circuit,” ACM Trans.on Embedded Computing Systems,doi:10.1145/1596543.1596548.

[17]L.Chua,“Memristor-the missing circuit element,” IEEE Trans.on Circuit Theory,vol.18,no.5,pp.507-519,1971.

[18]J.F.Scott,“Data storage:Multiferroic memories,” Nature Materials,vol.6,no.4,pp.256-257,2007.

[19]M.Gajek,M.Bibes,S.Fusil,K.Bouzehouane,J.Fontcuberta,A.Barthelemy,and A.Fert,“Tunnel junctions with multiferroic barriers,” Nature Materials,vol.6,no.4,pp.296-302,2007.

[20]C.Binek and B.Doudin,“Magnetoelectronics with magnetoelectrics,” Journal of Physics:Condensed Matter,doi:10.1088/0953-8984/17/2/L06.

[21]M.Vadizadeh,B.Davaji,and M.Fathipour,“New challenges on leakage current improvement in tunnel FET by using low-κ oxide,” in Proc.of the 1st Asia Symposium on Quality Electronic Design,Kuala Lumpur,2009,pp.136-139,.

[22]N.Weste and D.Harris,CMOS VLSI Design:A Circuits and Systems Perspective,Boston:Addison-Wesley Publishing Company,2010.

[23](Aug.2010).Int.Technology Roadmap for Semiconductors.[Online].Available:http://www.itrs.net.

[24]W.-S.Zhao,D.Querlioz,J.O.Klein,D.Chabi,and C.Chappert,“Nanodevice-based novel computing paradigms and the neuromorphic approach,” in Proc.of IEEE Int.Symposium on Circuits and Systems,Seoul,2012,pp.2509-2512.

[25]W.-S.Zhao,E.Belhaire,C.Chappert,F.Jacquet,and P.Mazoyer,“New non-volatile logic based on spin-MTJ,”Physica Status Solidi ,vol.205,no.6,pp.1373-1377,2008.

[26]D.Niu,Y.Chen,and Y.Xie,“Low-power dual-element memristor based memory design,” in Proc.of 2010 Int.Symposium on Low Power Electronics and Design,Austin,pp.25-30,2010.

[27]Y.Chen,X.Wang,H.Li,H.Xi,Y.Yan,and W.Zhu,“Design margin exploration of spin-transfer torque RAM(STT-RAM)in scaled technologies,” IEEE Trans.on Very Large Scale Integration(VLSI)Systems,vol.18,no.12,pp.1724-1734,2010.

[28]W.-S.Zhao,J.O.Klein,Z.Wang,Y.Zhang,N.Ben Romhane,D.Querlioz,et al.,“Spin-electronics based logic fabrics,” in Proc.of IFIP/IEEE the 21st Int.Conf.on Very Large Scale Integration(VLSI-SoC),Istanbul,2013,pp.174-179.

[29]S.-H.Kang,“Embedded STT-MRAM for mobile applications:Enabling advanced chip architectures,” preaent at the Non-Volatile Memories Workshop,San Diego,Apr.11-13,2010.

[30]H.Yoda,S.Fujita,N.Shimomura,E.Kitagawa,K.Abe,K.Nomura,et al.,“Progress of STT-MRAM technology and the effect on normally-off computing systems,” in Proc.of IEEE Int.Electron Devices Meeting,San Francisco,pp.11.3.1-11.3.4,2012.

[31]H.P.Trinh,W.-S.Zhao,J.O.Klein,Y.Zhang,D.Ravelsona,and C.Chappert,“Magnetic adder based on racetrack memory,” IEEE Trans.on Circuits and Systems I:Regular Papers,vol.60,no.6,pp.1469-1477,2013.

[32]W.-S.Zhao,L.Torres,L.V.Cargnini,R.M.Brum,Y.Zhang,Y.Guillemenet,and C.Chappert,“High performance SoC design using magnetic logic and memory,” in Proc.of IEEE Int.Conf.on VLSI-SoC:Advanced Research for Systems on Chip,Heidelberg,pp.10-33,2012.

[33]Y.Lakys,W.-S.Zhao,J.O.Klein,and C.Chappert,“Low power,high reliability magnetic flip-flop,” Electronics Letters,vol.46,no.22,pp.1493-1494,2010.

[34]J.M.Portal,M.Bocquet,D.Deleruyelle,and C.Muller,“Non-volatile flip-flop based on unipolar ReRAM for power-down applications,” Journal of Low Power Electronics,vol.8,no.1,pp.1-10,2012.

[35]Y.Zhang,W.-S.Zhao,G.Prenat,T.Devolder,J.O.Klein,C.Chappert,et al.,“Electrical modeling of stochastic spin transfer torque writing in magnetic tunnel junctions for memory and logic applications,” IEEE Trans.on Magnetics,vol.49,no.7,pp.4375-4378,2013.

[36]W.Kang,W.-S.Zhao,Z.Wang,Y.Zhang,J.O.Klein,Y.Zhang,et al.,“A low-cost built-in error correction circuit design for STT-MRAM reliability improvement,”Microelectronics Reliability,vol.53,no.9,pp.1224-1229,2013.

[37]P.Chow,S.O.Seo,J.Rose,K.Chung,G.Páez-Monzón,and I.Rahardja,“The design of an SRAM-based field-programmable gate array—part I:Architecture,” IE EE Trans.on Very Large Scale Integration(VLSI)Systems,vol.7,no.2,pp.191-197,1999.

[38]W.-S.Zhao,E.Belhaire,C.Chappert,B.Dieny,and G.Prenat,“TAS-MRAM-based low-power high-speed runtime reconfiguration (RTR) FPGA,” ACM Trans.on Reconfigurable Technology and Systems,doi:10.1145/1534916.1534918.

[39]G.Prenat,M.El Baraji,W.Guo,R.Sousa,L.Buda-Prejbeanu,B.Dieny,et al.,“CMOS/magnetic hybrid architectures,” in Proc.of the 14th IEEE Int.Conf.on Electronics,Circuits,and Systems,Marrakech,2007,pp.190-193.

[40]W.-S.Zhao,D.Ravelosona,J.O.Klein,and C.Chappert,“Domain wall shift register-based reconfigurable logic,”IEEE Trans.on Magnetics,vol.47,no.10,pp.2966-2969,2011.

[41]Y.Zhang,W.-S.Zhao,D.Ravelosona,J.O.Klein,J.V.Kim,and C.Chappert,“Perpendicular-magnetic-anisotropy CoFeB racetrack memory,” Journal of Applied Physics,vol.111,no.9,pp.093925,2012.

[42]W.-S.Zhao,N.Ben Romdhane,Y.Zhang,J.O.Klein,and D.Ravelosona,“Racetrack memory based reconfigurable computing,” in Proc.of IEEE Faible Tension Faible Consommation FTFC,Paris,2013,pp.1-4.

[43]C.Mead,“Neuromorphic electronic systems,” Proc.of the IEEE,vol.78,no.10,pp.1629-1636,1990.

[44]Y.V.Pershin and M.Di Ventra,“Neuromorphic,digital,and quantum computation with memory circuit elements,”Proc.of the IEEE,vol.100,no.6,pp.2071-2080,2012.

[45]A.Chanthbouala,V.Garcia,R.O.Cherifi,K.Bouzehouane,S.Fusil,X.Moya,et al.,“A ferroelectric memristor,”Nature Materials,vol.11,no.10,pp.860-864.2012.

[46]X.Wang,Y.Chen,H.Xi,H.Li,and D.Dimitrov,“Spintronic memristor through spin-torque-induced magnetization motion,” IEEE Electron Device Letters,vol.30,no.3,pp.294-297,2009.

[47]O.Bichler,W.-S.Zhao,F.Alibart,S.Pleutin,S.Lenfant,D.Vuillaume,and C.Gamrat,“Pavlov’s dog associative learning demonstrated on synaptic-like organic transistors,”Neural Computation,vol.25,no.2,pp.549-566,2013.

[48]S.-Y.Liao,J.M.Retrouvey,G.Agnus,W.-S.Zhao,C.Maneux,S.Frégonèse,et al.,“Design and modeling of a neuro-inspired Learning circuit using nanotube-based memory devices,” IEEE Trans.on Circuits and Systems I:Regular Papers,vol.58,no.9,pp.2172-2181,2011.

[49]D.Chabi,W.-S.Zhao,D.Querlioz,and J.O.Klein,“Robust neural logic block(NLB)based on memristor crossbar array,” in Proc.of IEEE/ACM Int.Symposium on Nanoscale Architectures,San Diego,2011,pp.137-143.

[50]G.S.Snider,“Spike-timing-dependent learning in memristive nanodevices,” in Proc.of IEEE Int.Symposium on Nanoscale Architectures,Anaheim,2008,pp.85-92.

[51]G.-Q.Bi and M.M.Poo,“Synaptic modification by correlated activity:Hebb’s postulate revisited,” Annual Review of Neuroscience,vol.24,no.1,pp.139-166,2001.

[52]Y.Zhang,W.-S.Zhao,J.O.Klein,W.Kang,D.Querlioz,Y.Zhang,et al.,“Spintronics for low-power computing,” in Proc.of Design,Automation and Test in Europe Conf.and Exhibition,Dresden,2014,pp.1-6.