Device physics and design of FD-SOI JLFET with step-gate-oxide structure to suppress GIDL effect∗

Bin Wang(王斌), Xin-Long Shi(史鑫龙), Yun-Feng Zhang(张云峰),Yi Chen(陈伊),2, Hui-Yong Hu(胡辉勇), and Li-Ming Wang(王利明)

1State Key Discipline Laboratory of Wide Bandgap Semiconductor Technology,School of Microelectronics,Xidian University,Xi’an 710071,China

2Mailbox 150,BaoJi 721000,China

Keywords: junctionless field-effect transistor(FET),gate-induced drain leakage(GIDL),step-gate-oxide,offstate current

1. Introduction

Scaled down into nanometers,conventional Si MOSFETs are facing the problems of forming ultra-steep doping profile in p–n junctions,[1–4]and field-effect transistors(FETs)without junctions,i.e.,junctionless FETs(JLFETs)were proposed to eliminate the stringent requirement.[5–10]Unlike “regular”p–n junction-based FET,the JLFET usually has the same uniform doping concentration in the source, channel and drain region. The metal with large work function is introduced as gate electrode to deplete the entire channel region at zero biased gate voltage (VGS=0 V).[11–13]In the on-state, the depletion region under the gate dies away and the entire channel region becomes neutral, allowing carriers to flow from drain to source. Therefore, the JLFET is working in the flatband mode or accumulation mode,which is very different from the inversion mode-mechanism of MOSFET. Due to these reasons, the JLFET fetures simplified fabrication process, large on-state current Ion,excellent drive capability and is a promising candidate as crucial components for the future electronics industry.

However, to ensure the full depletion of the channel by gate at zero bias, the gate electrode with large work function(such as 5.1 eV for n-JLFET, 4.3 eV for p-JLFET, etc.) and the channel with thin thickness is preferred. Thus, a serious gate-induced drain leakage(GIDL)effect is caused due to the considerable lateral band-to-band tunneling (L-BTBT)[14,15]at channel–drain surface in the off-state, thus increasing the off-state current Iofffinally.[16–18]

To suppress the GIDL effect in JLFET, several efforts have been made to reduce the tunneling probability T(E) of L-BTBT,such as JLFET with hole sink layer(HS JLFET),[19]JLFET with hetero-dielectric buried oxide(HDB JLFET),[20]JLFET with hetero-gate dielectric (HGD JLFET),[21]JLFET with dual material gate(DMG JLFET),[14]JLFET with coreshell architecture (CS JLFET),[22]JLFET with tunnel dielectric(TD JLFET),[23]etc.However,these devices usually cause other issues,hindering their applications. The HS JLFET consisting of a doped p–n junction suffers the creation of such an abrupt junction and its on-state current is low(∼3.3 times)as compared with the SOI JLFET’s.In the HDB JLFET,the interface between the high-k dielectric and SiO2in the buried oxide(BOX)region must be appropriately aligned with the channel–drain interface,which requires a stringent control of the wafer fabrication process. The HGD JLFET encountered the same issues, fabricating the hetero-gate dielectric and alignment of the hetero-dielectric interface in the middle of the channel region are the major issues concerning the HGD JLFETs. The DMG JLFET is also facing the fabrication problem, since achieving distinct gate materials within a span of 20 nm itself is a technological challenge. The CS JLFET also needs to create an abrupt junction at the core–shell interface through using the industry standard ion implantation process which is not feasible and has the same technological challenges faced while fabricating nanowires. Due to the defects and traps introduced by TD in the center of the channel, the TD JLFET faces the problems of dielectric semiconductor interface which should be further suppressed. To solve the issues above,we have proposed two types of JLFET based on fully depleted SOI (FDSOI) substrate with field plate (FP) structure[24]and lightly doped drain(LDD)structure,[25]respectively,to suppress the GIDL effect, but the FP structure needs additionally another type of metal to enhance the performance of the device, and LDD structure causes the on-state resistance to increase,thus reducing the on-state current of the device.

In this paper, a novel n-type JLFET based on FD-SOI with a step-gate-oxide (SGO) structure is proposed to suppress the GIDL effect and Ioff. With the help of step-gateoxide,the tunneling width in the region where drain and channel are overlapped is enlarged and the tunneling probability is reduced, which leads the GIDL current to be suppressed significantly. The Sentaurus simulation results indicate that the Ioffof the SGO-JLFET decreases significantly with little impaction on its on-state current Ionand threshold voltage VTH.So its Ion/Ioffratio is enhanced by 37 times compared with that of the normal JLFET, and subthreshold swing (SS) increases to 84 mV/dec. Meanwhile, the thicker tunnel-gateoxide can weaken the influence on the total gate capacitance of JLFET,which can alleviate the capacitive load of the transistor in the circuit applications. The influences of the structure of step-gate-oxide,such as TToxide(thickness of the tunnel oxide), LToxide(length of the tunnel oxide), LCoxide(length of the control oxide)are discussed in detail,which could provide useful instruction for the device design.

2. Device structure and simulation parameters

Figure 1 shows the cross-section of the normal JLFET and step-gate-oxide JLFET(SGO JLFET),respectively. Comparing with the normal JLFET,the gate oxide in the SGO JLFET is composed of two parts: control oxide and tunnel oxide.Just as in the normal JLFET, The control oxide near source region in the novel JLFET is used to shut down the device when VGS=0 V,and the tunnel oxide near drain region is used to reduce the tunneling probability T(E)of L-BTBT between channel and drain. When VGSis increasing, the depletion region under tunnel oxide vanishes first, and then the depletion region under control oxide vanishes,turning the device on.

The simulation device parameters are listed in Table 1.Simulations are carried out by using the Sentaurus TCAD.In the simulations, the length and thickness of the tunnel oxide are chosen to be 10 nm and 6 nm,respectively,and the thickness of control oxide and channel are 3 nm and 7 nm,respectively. The channel of the normal JLFET and novel JLFET are uniformly doped (1×1019cm−3) and the metal of gate electrode is Au to ensure that the channel is fully depleted in offstate. High-k material of HfO2 is used as gate dielectric for both control oxide and tunnel oxide.

Fig.1. Cross-section of device structures of(a)normal JLFET and(b)SGO JLFET.

Table 1. Simulated device parameters used in this study.

The simulation models used in Ref. [26] are implanted into our simulations. The nonlocal BTBT model is considered for the band-to-band tunneling of charge carriers between drain and channel. Due to the high doping level,the bandgap narrowing(BGN)model is also included,because the effective bandgap directly influences the tunneling current. Also, the Shockley–Read–Hall(SRH)recombination model is included due to the presence of high impurity atom concentration in the channel,and Fermi–Dirac statistics is included to calculate the intrinsic carrier concentration. For more accurate current calculations,the field-dependent and doping-dependent mobility degradation models and the drift-diffusion current transport model,are also considered.

3. Results and discussion

Figure 2 shows the transfer curves of normal JLFET and SGO JLFET. For normal JLFET at VDS=1 V, with the decrease of the gate voltage VGS,the drain current first decreases until it reaches its minimum value,and then starts to increase again due to GIDL effect,resulting in an off-state current with a value of 4.4×10−7A/µm. However,for the SGO JLFET,an off-state current of 1.23×10−8A/µm is achieved at VGS=0 V,VDS=1 V due to step-gate-oxide structure, decreased by 37 times compared with that in normal JLFET.Meanwhile,since the little influence of step-gate-oxide on channel in the onstate, both of the extracted threshold voltage (VTH) of SGO JLFET and normal JLFET are 0.25 V by the trans-conductance(gm)derivative method atVDS=0.1 V,[27]and the on-state current remains almost the same(6×10−4A/µm)compared with that in the normal JLFET.Therefore,the SGO JLFET exhibits a high Ion/Ioffratio(5×104)compared with the normal JLFET(1.4×103). The extracted average subthreshold swing(SS)of SGO JLFET is 84mV/decade,which is also much better than the value of 190 mV/decade in normal JLFET.

Fig.2. Transfer characteristics of normal JLFET and SGO JLFET.

Figure 3 shows the comparison of the energy band diagram at the surface of the SGO JLFET with that at the surface of normal JLFET at VDS= 1 V, VGS= 0 V. The Tw1and Tw2represent the tunneling width of normal JLFET and SGO JLFET respectively. It can be observed that Tw2is much larger than Tw1. An enlarged tunneling width leads the tunneling of electrons from the channel region to the drain region to decrease, resulting in a significantly reduced BTBT probability T(E) as shown in Fig.4. Figure 4 shows the surface BTBT probability at channel–drain interface between the SGO JLFET and normal JLFET when VDS=1 V and VGS=0 V.It can be seen that the largest T(E)in the SGO JLFET reduces about 5 orders of magnitude over that in the normal JLFET.

Fig.3. Surface band diagram of normal JLFET and SGO JLFET at VDS=1 V and VGS=0 V.

Fig.4. Surface BTBT probability plot at gate/drain interface when VDS =1 V and VGS=0 V.

Figure 5 shows the curve of surface hole density versus VGSin the channel of SGO JLFET and normal JLFET at VGS=0 V, VDS=1 V. It can be clearly seen that the value of hole density under tunnel oxide in the SGO JLFET is much lower than that in the same region of the normal JLFET,resulting in the enlargement of tunneling width as shown in Fig.3.Meanwhile,it can be seen that the hole density under the control oxide in the SGO JLFET is also less than that in the normal JLFET,which is mainly caused by the reduction of total gate capacitance(Cgg).

Fig.5. Surface hole concentration of normal JLFET and SGO JLFET at VGS=0 V and VDS=1 V.

It can be seen from Eqs. (1) and (2) that a larger TToxideresults in a less value of Cgg. Therefore,the total gate capacitance of SGO JLFET is smaller than that of normal JLFET as shown in Fig.6.

Fig.6. Total gate capacitance of normal JLFET and SGO JLFET.

To show the influence of step-gate-oxide structure on Ioffmore clearly, the variation of the IDS–VGScurves with TToxideare simulated and shown in Fig.7. It can be seen from the figure that the off-state current decreases from 4.4×10−7A/µm to 1.2×10−8A/µm without sacrificing the on-state current as TToxideincreases from 3 nm to 6 nm. Since the increment increase of TToxidereduces the surface hole density under the tunnel oxide,the GIDL in SGO JLFET is inhibited and then Ioffdecreases as discussed above. With the increase of TToxide,the value of SS gradually decreases from 190 mV/dec to 84 mV/dec,and the Ion/Ioffratio increases from 1.3×104to 4.9×104as shown in Fig.8.

Fig.7. Variation of IDS–VGS curves with VGS for different values of TToxide in SGO JLFET.

Fig.8. Variation of SS and Ion/Ioff ratio with TToxide in SGO JLFET.

Figures 9 and 10 show the influence of LToxideon IDS–VGS,SS,and Ion/Ioffratio at VDS=1 V clearly.A larger LToxideresults in a wider tunnel path at VGS=0 V,and restricts GIDL more significantly. So,when LToxideis changed from 5 nm to 10 nm, the off-state current Ioffof SGO JLFET at VGS=0 V decreases from 5×10−8A/µm to 1.23×10−8A/µm with influence on the on-state current weakening, thus, reducing the SS from 109 mV/dec to 84 mV/dec and increasing the Ion/Ioffratio from 1.2×104to 5×104as shown in Fig.10. However,A larger LToxideshortens the length of control oxide due to Lch=LToxide+LCoxide, which means the effective depletion length of channel determined by LCoxidein the off-state decreases with the LToxideincreasing,so the off-state current Ioffincreases again and obtains a value of 3.24×10−8A/µm, the SS and Ion/Ioffratio reach a value of 91 mV/dec and 1.9×104at LToxide=20 nm,respectively.

Fig.9. Variations of ID–VGS curves for different values of LToxide in SGO JLFET.

Fig.10. SS and Ion/Ioff ratio versus LToxide in SGO JLFET.

To clearly show the influence of LCoxideon the performance of the SGO JLFET,the IDS–VGScurves of SGO JLFET with LCoxidechanging from 10 nm to 30 nm in steps of 10 nm are shown in Fig.11.As indicated in Fig.11,the change of the control gate length LCoxidehas little effect on the on-state current. However,since the length of depletion region under control oxide decreases with LCoxidedecreasing,the off-state current Ioffchanges from 1.23×10−8A/µm to 1.03×10−5A/µm,and the Ion/Ioffratio changes from 5×104to 59,thereby deteriorating the performance of the SGO JLFET.

Figure 12 shows the output characteristics of the SGO JLFET with different gate voltages. The drain current IDSseparately at VGS=0.25 V, 0.5 V, 0.75 V, and 1 V first increases and then reaches saturation at high drain voltages,and IDSat VDS= 1 V increases from 1.12×10−5A/µm to 6.12×10−4A/µm as VGSincreases from 0.25 V to 1 V,showing good conduction characteristics.

Fig.11. Transfer curves for different values of LCoxide in SGO JLFET.

Fig.12. IDS–VDS curves in SGO JLFET for different values of VGS.

4. Conclusions

In this paper,a novel FD-SOI JLFET with step-gate-oxide structure is proposed to improve the I–V performance. Using the Sentaurus TCAD tool, the new step-gate-oxide architecture is demonstrated to be able to effectively broaden the tunneling width of L-BTBT in the drain–channel overlap region,thereby reastricting the GIDL effect. Thus, compared with the normal JLFETs,the proposed architecture reduces the offstate current and does not deteriorate the on-state current or VTH, resulting in a significant enhancement of SS and Ion/Ioffratio. The influence of TToxide,LToxide,and LCoxideon the performance of SGO JLFET are also examined,which could provide useful instructions for designing the device.